In recent years, a panel display apparatus such as a liquid crystal display apparatus has been developed to have a finer resolution and a larger screen size, and as a result of this, a source driver for driving the display panel is required to have a capability of driving a large capacitive load at a higher speed. Therefore, it is necessary to improve a slew rate of a differential amplifier circuit used in an output stage of the source driver.
On the other hand, in a market of a cellular phone and other portable equipment with a built-in panel display apparatus, a demand of low current consumption amount is increased in order to extend a battery drive period. Since several tens to several hundreds of differential amplifier circuits are used according to a size of a display panel in the source driver of the panel display apparatus, it is important to reduce a current consumption amount per a single differential amplifier circuit.
One technique for realizing a high slew rate is to increase a bias current to be supplied to a differential pair in the input stage of the differential amplifier circuit. If the bias current is increased, a mutual conductance gm of each transistor of the differential pair is increased so that the high slew rate can be realized. However, this technique is involved with a problem that the current consumption amount of the differential amplifier circuit is increased.
In order to realize the high slew rate while suppressing the increase of the current consumption amount, in one technique, the bias current to be supplied to the differential pair in the input stage is increased only when signal levels of an inversion input signal and a non-inversion input signal is altered. Such a differential amplifier circuit is disclosed in JP 2001-156559A (Patent Literature 1).
FIG. 6 is a circuit diagram showing a configuration of the differential amplifier circuit disclosed in JP 2001-156559A. The differential amplifier circuit shown in FIG. 6 includes a PMOS differential input section 1, an NMOS differential input section 2, current mirror circuits 3 and 4, a push-pull output stage 5, a PMOS sub current source 6 and an NMOS sub current source 7.
The PMOS differential input section 1 includes PMOS transistors M1, M2 and M3. The PMOS transistors M2 and M3 have their sources connected in common and configure a differential transistor pair. A gate of the PMOS transistor M2 is connected to an inversion input In− and the gate of the PMOS transistor M3 is connected to a non-inversion input In+. The gate of the PMOS transistor M1 is supplied with a bias voltage Vb1 so as to supply a bias current to the PMOS transistors M2 and M3. Output signals of the PMOS differential input section 1 from the PMOS transistors M2 and M3 are supplied to the current mirror circuit 4.
Meanwhile, the NMOS differential input section 2 includes NMOS transistors M4, M5 and M6. The NMOS transistors M4 and M5 have their sources connected in common and configure a differential transistor pair. A gate of the NMOS transistor M4 is connected to the inversion input In− and a gate of the NMOS transistor M5 is connected to the non-inversion input In+. The gate of the NMOS transistor M6 is supplied with a bias voltage Vb2 so as to supply bias current to the NMOS transistors M4 and M5. Output signals of the NMOS differential input section 2 from the NMOS transistors M4 and M5 are supplied to the current mirror circuit 3.
The current mirror circuit 3 includes PMOS transistors M7, M8, M9 and M10 in which the gates of the PMOS transistors M9 and M10 are supplied with a bias voltage Vb3. Meanwhile, the current mirror circuit 4 includes NMOS transistors M11, M12, M13 and M14 in which the gates of the NMOS transistors M11 and M12 are supplied with a bias voltage Vb4. The current mirror circuit 3 and the current mirror circuit 4 are connected via resistor elements R101 and R102. The resistor elements R101 and R102 may be replaced with MOS transistors and the like.
The push-pull output stage 5 includes a PMOS output transistor M15 and an NMOS output transistor M16, and is connected to an output terminal Vout. A gate of the PMOS output transistor M15 is connected to a connection node between the PMOS transistor M10 and one end of the resistor element R102. A gate of the NMOS output transistor M16 of the push-pull output stage 5 is connected to a connection point between the NMOS transistor M12 and the other end of the resistor element R102. In addition, a phase compensating capacitor C101 is connected between an output terminal Vout and a source of the PMOS transistor M10, and a phase compensating capacitor C2 is connected between the output terminal Vout and the source of the NMOS transistor M12.
The PMOS sub current source 6 includes a PMOS sub current source transistor M18 and the gate thereof is supplied with a gate voltage of the PMOS output transistor M15. The PMOS sub current source 6 is connected in parallel with the PMOS transistor M1 of the PMOS differential input section 1. Similarly, the NMOS sub current source 7 includes an NMOS sub current source transistor M19 and the gate thereof is supplied with a gate voltage of the NMOS output transistor M16 of the push-pull output stage 5. The NMOS sub current source 7 is connected in parallel with the NMOS transistor M6 of the NMOS differential input section 2.
In FIG. 6, a symbol CL denotes an external load connected to the output terminal Vout of the push-pull output stage 5, a symbol Vdd denotes a positive power source line, and a symbol Vss denotes a negative power source line.
The differential amplifier circuit shown in FIG. 6 operates as described below. That is, a high output slew rate is realized while suppressing an increase of the current consumption amount. Specifically, when an operation state is changed from a steady state to a state that the non-inversion input voltage Vin+ is higher in level than the inversion input voltage Vin−, the PMOS sub current source transistor M18 is turned on so that the PMOS sub current source 6 is operated. Thus, the bias current of the PMOS differential input section 1 is temporarily increased. Similarly, when an operation state is changed from a steady state to a state that the non-inversion input voltage Vin+ is lower in level than the inversion input voltage Vin−, the NMOS sub current source transistor M19 is turned on so that the NMOS sub current source 7 is operated. Thus, the bias current of the NMOS differential input section 2 is temporarily increased. In either case, when there is a change in the non-inversion input voltage Vin+ and the inversion input voltage Vin−, the bias current is temporarily increase to thereby realize a high slew rate. On the other hand, since the increase of the bias current is temporary, increase of the current consumption amount can be suppressed.